Presentation	2014-01-29 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4V) Operation H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (V_ ). In the ultralow-V_ regime, however, the upsurging delay (τ_) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at V_ = 0.4 V.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SOTB / SOI / back bias / ring oscillator / τ_ / variability / ultra-low voltage
Paper #	SDM2013-143
Date of Issue

Conference Information
Committee	SDM
Conference Date	2014/1/22(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Silicon Device and Materials (SDM)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4V) Operation
Sub Title (in English)
Keyword(1)	SOTB
Keyword(2)	SOI
Keyword(3)	back bias
Keyword(4)	ring oscillator
Keyword(5)	τ_
Keyword(6)	variability
Keyword(7)	ultra-low voltage
1st Author's Name	H. Makiyama
1st Author's Affiliation	Low-power Electronics Association & Project()
2nd Author's Name	Y. Yamamoto
2nd Author's Affiliation	Low-power Electronics Association & Project
3rd Author's Name	H. Shinohara
3rd Author's Affiliation	Low-power Electronics Association & Project
4th Author's Name	T. Iwamatsu
4th Author's Affiliation	Low-power Electronics Association & Project
5th Author's Name	H. Oda
5th Author's Affiliation	Low-power Electronics Association & Project
6th Author's Name	N. Sugii
6th Author's Affiliation	Low-power Electronics Association & Project
7th Author's Name	K. Ishibashi
7th Author's Affiliation	The University of Electro-Communications
8th Author's Name	T. Mizutani
8th Author's Affiliation	The University of Tokyo
9th Author's Name	T. Hiramoto
9th Author's Affiliation	The University of Tokyo
10th Author's Name	Y. Yamaguchi
10th Author's Affiliation	Low-power Electronics Association & Project
Date	2014-01-29
Paper #	SDM2013-143
Volume (vol)	vol.113
Number (no)	420
Page	pp.pp.-
#Pages	4
Date of Issue