Presentation 2013-09-27
LSI Implementation of a Secure Low-Power CSSAL Cellular Multiplier
Cando MONTEIRO, Yasuhiro TAKAHASHI, Toshikazi SEKINE,
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Abstract(in English) In this paper, a secure and low-power charge-sharing symmetric adiabatic logic cellular multiplier over GF(2^4) implemented in LSI using 0.18um CMOS process is presented. The verification of the logic functionality and the operating speed of the implemented LSI in adiabatic switching technique will be discussed. The correlation of LSI output logic function and the supply current trace are measured in order to analyze the current-to-data dependency in respect to the given input transitions. Maximum power clock frequency for chip measurement is 5 MHz, whereas the post-layout simulation is up to 50 MHz and the pre-layout simulation reaches 125 MHz using the same individual logic.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) adiabatic / bit-parallel multiplier / SCA / cryptographic
Paper # CAS2013-52,NLP2013-64
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Conference Information
Committee NLP
Conference Date 2013/9/19(1days)
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Registration To Nonlinear Problems (NLP)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) LSI Implementation of a Secure Low-Power CSSAL Cellular Multiplier
Sub Title (in English)
Keyword(1) adiabatic
Keyword(2) bit-parallel multiplier
Keyword(3) SCA
Keyword(4) cryptographic
1st Author's Name Cando MONTEIRO
1st Author's Affiliation Graduate School of Engineering, Gifu University, Japan()
2nd Author's Name Yasuhiro TAKAHASHI
2nd Author's Affiliation Faculty Engineering, Gifu University, Japan
3rd Author's Name Toshikazi SEKINE
3rd Author's Affiliation Faculty Engineering, Gifu University, Japan
Date 2013-09-27
Paper # CAS2013-52,NLP2013-64
Volume (vol) vol.113
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue