Presentation | 2013-09-27 Evaluation of Synaptic Weighting Circuit with Pulse-Based Memristor using Adibatic Driving Haruki OGATA, Yasuhiro TAKAHASHI, Toshikazu SEKINE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In the implementation of neural network system, the problem is that the system has large area and high power consumption. To solve a reduction of LSI area, the synaptic circuit using a memristor has been proposed. The feature of this circuit is a small circuit area compared with conventional CMOS. However, the synaptic circuit having low power consumption is not still proposed. This paper reports that the synaptic circuit using a memristor is applied with adiabatic logic technology and then the proposed circuit has a low power dissipation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Memristor / Synaptic circuit / Low power / Adiabatic logic technology / Neural network |
Paper # | CAS2013-51,NLP2013-63 |
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Committee | NLP |
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Conference Date | 2013/9/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Nonlinear Problems (NLP) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Evaluation of Synaptic Weighting Circuit with Pulse-Based Memristor using Adibatic Driving |
Sub Title (in English) | |
Keyword(1) | Memristor |
Keyword(2) | Synaptic circuit |
Keyword(3) | Low power |
Keyword(4) | Adiabatic logic technology |
Keyword(5) | Neural network |
1st Author's Name | Haruki OGATA |
1st Author's Affiliation | Graduate School of Engineering, Gifu University() |
2nd Author's Name | Yasuhiro TAKAHASHI |
2nd Author's Affiliation | Faculty of Engineering, Gifu University |
3rd Author's Name | Toshikazu SEKINE |
3rd Author's Affiliation | Faculty of Engineering, Gifu University |
Date | 2013-09-27 |
Paper # | CAS2013-51,NLP2013-63 |
Volume (vol) | vol.113 |
Number (no) | 225 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |