Presentation 2013-09-27
Operation Verification of Adiabatic Logic in Subthreshold Region
Kazunari KATO, Yasuhiro TAKAHASHI, Toshikazu SEKINE,
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Abstract(in English) Our previously proposed ultra low-power sub-threshold adiabatic logic has been a problem that noise margin is reduced, so that it is impossible to implement a cascade connection. In this paper, we propose a novel sub-threshold adiabatic logic which uses a diode connected MOS transistor. By using a diode the noise margin of output is improved. To evaluate our proposed circuit, an inverter, NAND, NOR, and XOR logic are designed, and then the operation function and power dissipation are confirmed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) sub-threshold / adiabatic logic / two-pahse clocking / energy harvesting
Paper # CAS2013-50,NLP2013-62
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Conference Information
Committee NLP
Conference Date 2013/9/19(1days)
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Registration To Nonlinear Problems (NLP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Operation Verification of Adiabatic Logic in Subthreshold Region
Sub Title (in English)
Keyword(1) sub-threshold
Keyword(2) adiabatic logic
Keyword(3) two-pahse clocking
Keyword(4) energy harvesting
1st Author's Name Kazunari KATO
1st Author's Affiliation Graduate School of Engineering, Gifu University()
2nd Author's Name Yasuhiro TAKAHASHI
2nd Author's Affiliation Faculty of Engineering, Gifu University
3rd Author's Name Toshikazu SEKINE
3rd Author's Affiliation Faculty of Engineering, Gifu University
Date 2013-09-27
Paper # CAS2013-50,NLP2013-62
Volume (vol) vol.113
Number (no) 225
Page pp.pp.-
#Pages 6
Date of Issue