| Presentation | 2013-09-26 Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method Daisei NAGATA, Tadatoshi SEKINE, Hideki ASAI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distribution networks (PDNs) with power/ground through silicon vias (P/G TSVs).The block-LIM has been proposed as a fast circuit simulation approach for large networks including a number of coupling elements such as mutual inductances and mutual capacitances. The block-LIM can simulate the on-chip PDNs with P/G TSVs, because they are modeled as equivalent circuits including mutual coupling elements. Numerical results show that the block-LIM can reduce the computational cost compared with HSPICE in the simulation of the equivalent circuit of the on-chip PDN with the P/G TSVs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | block latency insertion method (block-LIM) / latency insertion method (LIM) / power/ground through silicon via (P/G TSV) / three-dimensional stacked on-chip power distribution network (PDN) |
| Paper # | CAS2013-36,NLP2013-48 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2013/9/19(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method |
| Sub Title (in English) | |
| Keyword(1) | block latency insertion method (block-LIM) |
| Keyword(2) | latency insertion method (LIM) |
| Keyword(3) | power/ground through silicon via (P/G TSV) |
| Keyword(4) | three-dimensional stacked on-chip power distribution network (PDN) |
| 1st Author's Name | Daisei NAGATA |
| 1st Author's Affiliation | Dept. of Mechanical Eng., Graduate School of Eng., Shizuoka University() |
| 2nd Author's Name | Tadatoshi SEKINE |
| 2nd Author's Affiliation | Dept. of Mechnaical Eng., Shizuoka University |
| 3rd Author's Name | Hideki ASAI |
| 3rd Author's Affiliation | Nanovision Research Division, Shizuoka University |
| Date | 2013-09-26 |
| Paper # | CAS2013-36,NLP2013-48 |
| Volume (vol) | vol.113 |
| Number (no) | 225 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |