Presentation 2013-10-24
Symbolic Model Checking of Embedded CISC Assembly Program
Kenta WATANABE, Hyejin JANG, Kohei SAKURAI, Satoshi YAMANE,
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Abstract(in English) The more complicated embedded systems are, the more difficult verification of safety and reliability is. Therefore, the formal verification, which can prove rightness automatically, attracts attention as an exhaustive verification method for programs. This research provides effective formal verification method of hardware-dependence, for example, stack overflow and multiplex interruption.
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Keyword(in English) Embedded System / Microcontroller / Assembly Program / Model Checking
Paper # SS2013-36
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Committee SS
Conference Date 2013/10/17(1days)
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Registration To Software Science (SS)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Symbolic Model Checking of Embedded CISC Assembly Program
Sub Title (in English)
Keyword(1) Embedded System
Keyword(2) Microcontroller
Keyword(3) Assembly Program
Keyword(4) Model Checking
1st Author's Name Kenta WATANABE
1st Author's Affiliation Division of Electrical Engineering and Computer Science, Graduate School of Natural Science and Technology, Kanazawa University()
2nd Author's Name Hyejin JANG
2nd Author's Affiliation Division of Electrical Engineering and Computer Science, Graduate School of Natural Science and Technology, Kanazawa University
3rd Author's Name Kohei SAKURAI
3rd Author's Affiliation Faculty of Electrical and Computer Engineering, Institute of Science and Engineering, Kanazawa University
4th Author's Name Satoshi YAMANE
4th Author's Affiliation Faculty of Electrical and Computer Engineering, Institute of Science and Engineering, Kanazawa University
Date 2013-10-24
Paper # SS2013-36
Volume (vol) vol.113
Number (no) 269
Page pp.pp.-
#Pages 5
Date of Issue