Presentation 2013-10-08
A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage
Nobuaki Kobayashi, Tadayoshi Enomoto,
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Abstract(in English) We developed and applied a new circuit, called the "Self-controllable Voltage Level (SVL)" circuit, to achieve an expanded "read" margin in a low supply voltage 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the word-line voltages for a "read" and "write" operation, respectively. At the threshold voltage fluctuation of 6o, an operating VDD range was less than 1.15 V at the "read" margin of 0 V for the conventional SRAM, while on the other hand, the operating VDD range was less than 0.59 V at that for the newly developed SRAM. This result showed that the SVL circuit can significantly expand the "read" margin of the SRAM. An area overhead was 0.677% that of the cony. SRAM.
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Keyword(in English) CMOS / SRAM / "read" margin / self-controllable voltage level circuit
Paper # VLD2013-58,ICD2013-82,IE2013-58
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Committee ICD
Conference Date 2013/9/30(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage
Sub Title (in English)
Keyword(1) CMOS
Keyword(2) SRAM
Keyword(3) "read" margin
Keyword(4) self-controllable voltage level circuit
1st Author's Name Nobuaki Kobayashi
1st Author's Affiliation Graduate School of Science and Engineering, Chuo University()
2nd Author's Name Tadayoshi Enomoto
2nd Author's Affiliation Graduate School of Science and Engineering, Chuo University
Date 2013-10-08
Paper # VLD2013-58,ICD2013-82,IE2013-58
Volume (vol) vol.113
Number (no) 236
Page pp.pp.-
#Pages 6
Date of Issue