Presentation | 2013-10-08 New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu BAI, Michitaka KAMEYAMA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary data can be transferred from two cells to one common adjacent cell simultaneously at each X intersection, which leads to area-efficient data transfer without reducing performance. Each cell is composed of a switch block and a logic block. Multiple-valued signaling is utilized to implement a compact switch block. In each logic block, differential-pair circuits are used to realize low-power logic operations including threshold operations, an arbitrary 2-variable binary function and a bit-serial addition. Moreover, a current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is utilized to reduce the current source count for low power. As a result, the area and power consumption of the multiple-valued reconfigurable VLSI is reduced to 60% and 82% in comparison with that of an equivalent CMOS reconfigurable VLSI, respectively, while the delay is kept same. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Multiple-valued logic / Reconfigurable VLSI / X-net / Current-mode logic / Current-source sharing technique |
Paper # | VLD2013-57,ICD2013-81,IE2013-57 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2013/9/30(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic |
Sub Title (in English) | |
Keyword(1) | Multiple-valued logic |
Keyword(2) | Reconfigurable VLSI |
Keyword(3) | X-net |
Keyword(4) | Current-mode logic |
Keyword(5) | Current-source sharing technique |
1st Author's Name | Xu BAI |
1st Author's Affiliation | Graduate School of Information Science, Tohoku University() |
2nd Author's Name | Michitaka KAMEYAMA |
2nd Author's Affiliation | Graduate School of Information Science, Tohoku University |
Date | 2013-10-08 |
Paper # | VLD2013-57,ICD2013-81,IE2013-57 |
Volume (vol) | vol.113 |
Number (no) | 236 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |