Presentation | 2013-10-08 A Bi-Linear Interpolation Unit Using Selector Logics Masashi SHIO, Masao YANAGISAWA, Nozomu TOGAWA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Bi-Linear interpolation is one of interpolation techniques, which interpolates a value linearly from itsfour circumferences. Bi-Linear interpolation is often used for image scaling and correction of distortion. In this paper, we propose a high-speed bi-linear interpolation circuit reducing carry propagation delay by using selector logics. We have implemented our bi-linear interpolation circuit in several ways and evaluated each of them. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Selector Logics / Interpolation / Linear Interpolation / Bi-Linear Interpolation |
Paper # | VLD2013-56,ICD2013-80,IE2013-56 |
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Committee | ICD |
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Conference Date | 2013/9/30(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Bi-Linear Interpolation Unit Using Selector Logics |
Sub Title (in English) | |
Keyword(1) | Selector Logics |
Keyword(2) | Interpolation |
Keyword(3) | Linear Interpolation |
Keyword(4) | Bi-Linear Interpolation |
1st Author's Name | Masashi SHIO |
1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
2nd Author's Name | Masao YANAGISAWA |
2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
3rd Author's Name | Nozomu TOGAWA |
3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
Date | 2013-10-08 |
Paper # | VLD2013-56,ICD2013-80,IE2013-56 |
Volume (vol) | vol.113 |
Number (no) | 236 |
Page | pp.pp.- |
#Pages | 6 |
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