| Presentation | 2013-10-08 A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations Yuta HAGIO, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. Thus, we have proposed a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. In this paper, we evaluate our high-level synthesis algorithm comparing several existing algorithms considering several situations. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Process and Delay Variation / Post-Silicon Tuning / High-Level Synthesis |
| Paper # | VLD2013-54,ICD2013-78,IE2013-54 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2013/9/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations |
| Sub Title (in English) | |
| Keyword(1) | Process and Delay Variation |
| Keyword(2) | Post-Silicon Tuning |
| Keyword(3) | High-Level Synthesis |
| 1st Author's Name | Yuta HAGIO |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2013-10-08 |
| Paper # | VLD2013-54,ICD2013-78,IE2013-54 |
| Volume (vol) | vol.113 |
| Number (no) | 236 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |