Presentation	2013-10-07 Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit Atsushi ITO, Makoto IKEDA,
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Abstract(in English)	With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inherent robustness. However design flow for the circuit have not been automated. We propose synthesizing a synchronous gate level description from RTL description by a commercial logic synthesis tool and converting to self synchronous circuit. Also we designed a standard cell library of self synchronous circuit and performed place and route. Post-layout simulation was shown.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	dual pipeline / self synchronous / automated design flow
Paper #	VLD2013-48,ICD2013-72,IE2013-48
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Conference Information
Committee	ICD
Conference Date	2013/9/30(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit
Sub Title (in English)
Keyword(1)	dual pipeline
Keyword(2)	self synchronous
Keyword(3)	automated design flow
1st Author's Name	Atsushi ITO
1st Author's Affiliation	The Univ. of Tokyo()
2nd Author's Name	Makoto IKEDA
2nd Author's Affiliation	The Univ. of Tokyo
Date	2013-10-07
Paper #	VLD2013-48,ICD2013-72,IE2013-48
Volume (vol)	vol.113
Number (no)	236
Page	pp.pp.-
#Pages	6
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