Presentation 2014-01-28
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption
Tomoya TASAKI, Hiroto KAGOTANI, Yuji SUGIYAMA,
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Abstract(in English) As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been proposed. However, the size of circuits synthesized by this algorithm tends to be large because it assumes QDI delay model. Yoshitake proposed a reduction method using a characteristic of a maximum delay loop in a dependency graph under SDI delay model. In this paper, we improve the method by extending the application range to dependency graphs that have multiple maximum delay loop.
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Keyword(in English) Asynchronous circuit / Dependency graph / QDI delay model / SDI delay model / Maximum delay loop
Paper # VLD2013-109,CPSY2013-80,RECONF2013-63
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Committee RECONF
Conference Date 2014/1/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption
Sub Title (in English)
Keyword(1) Asynchronous circuit
Keyword(2) Dependency graph
Keyword(3) QDI delay model
Keyword(4) SDI delay model
Keyword(5) Maximum delay loop
1st Author's Name Tomoya TASAKI
1st Author's Affiliation Graduate School of Natural Science Technology, Okayama University()
2nd Author's Name Hiroto KAGOTANI
2nd Author's Affiliation Graduate School of Natural Science Technology, Okayama University
3rd Author's Name Yuji SUGIYAMA
3rd Author's Affiliation Graduate School of Natural Science Technology, Okayama University
Date 2014-01-28
Paper # VLD2013-109,CPSY2013-80,RECONF2013-63
Volume (vol) vol.113
Number (no) 418
Page pp.pp.-
#Pages 6
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