Presentation 2014-01-28
Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench
Naru SUGIMOTO, Keimei MIYAJIMA, Takuya KUHARA, Takuzi MITUISHI, Hideharu AMANO,
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Abstract(in English) This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using the miniMax algorithm with alpha-beta pruning. In addition, HLS tool called CyberWorkBench (CWB) is used to implement hardware. By making the use of functions in CWB, parallel fully pipelined design is generated. The implemented solver works at 100MHz with Xilinx Spartan-6 XC6SLX45 FPGA on the Digilent Atlys board. It can search states after three moves in most cases.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) High Level Synthesis / Cyber Work Bench / FPGA / Blokus Duo
Paper # VLD2013-104,CPSY2013-75,RECONF2013-58
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Committee RECONF
Conference Date 2014/1/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench
Sub Title (in English)
Keyword(1) High Level Synthesis
Keyword(2) Cyber Work Bench
Keyword(3) FPGA
Keyword(4) Blokus Duo
1st Author's Name Naru SUGIMOTO
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Keimei MIYAJIMA
2nd Author's Affiliation Faculty of Science and Technology, Keio University
3rd Author's Name Takuya KUHARA
3rd Author's Affiliation Faculty of Science and Technology, Keio University
4th Author's Name Takuzi MITUISHI
4th Author's Affiliation Faculty of Science and Technology, Keio University
5th Author's Name Hideharu AMANO
5th Author's Affiliation Faculty of Science and Technology, Keio University
Date 2014-01-28
Paper # VLD2013-104,CPSY2013-75,RECONF2013-58
Volume (vol) vol.113
Number (no) 418
Page pp.pp.-
#Pages 6
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