Presentation 2014-01-28
Design and Implementation of High-Level Synthesis Compiler for Stream Computation
Ryo ITO, Hayato SUZUKI, Ryotaro CHIBA, Kentaro SANO, Satoru YAMAMOTO,
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Abstract(in English) High-level synthesis (HLS) has been getting more and more important as FPGAs are more widely used for various applications. Productivity improvement is now strongly demanded so that we can reduce time from algorithm design to hardware implementation, particularly, in the development of our custom stream computing processor with FPGAs. To obtain higher productivity, we propose an HLS compiler, a stream processor generator (SPGen), which generates HDL codes for stream computation with given equations. In this paper, we describe purpose, requirements, and implementation of SPGen.
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Keyword(in English) high-performance computation / high level synthesis / custom stream computation / FPGA
Paper # VLD2013-102,CPSY2013-73,RECONF2013-56
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Committee RECONF
Conference Date 2014/1/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Implementation of High-Level Synthesis Compiler for Stream Computation
Sub Title (in English)
Keyword(1) high-performance computation
Keyword(2) high level synthesis
Keyword(3) custom stream computation
Keyword(4) FPGA
1st Author's Name Ryo ITO
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Hayato SUZUKI
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Ryotaro CHIBA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
4th Author's Name Kentaro SANO
4th Author's Affiliation Graduate School of Information Sciences, Tohoku University
5th Author's Name Satoru YAMAMOTO
5th Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2014-01-28
Paper # VLD2013-102,CPSY2013-73,RECONF2013-56
Volume (vol) vol.113
Number (no) 418
Page pp.pp.-
#Pages 6
Date of Issue