| Presentation | 2013-10-03 TMR execution on SmartCore system for dependable many-core processors Ryosuke SASAKAWA, Shimpei SATO, Kenji KISE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to improve the chip-level dependability, we have proposed Smart Core system, NoC-based DMR(Dual Modular Redundant) mechanism by employing inherent redundancies of PEs in many-core processors. We also have proposed a multifunction on-chip router architecture that has additional capabilities to support DMR execution such as packet rendezvous and packet comparison. In this paper, we propose packet traverse rule and a multifunction router in order to support TMR(Triple Modular Redundant) execution. The packet traverse rule and the multifunction router for TMR execution is based on that of DMR execution. We evaluated the network performance in TMR execution by using several common network traffic patterns. The evaluation result shows that the increase of latency by TMR execution is about twice as long as the increase of latency by DMR execution. We also confirm that there is the allocation of TMR node parties which doesn't show worse throughput. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network on Chip / Many-core Processor / Triple Modular Redundancy / Network Performance |
| Paper # | CPSY2013-32 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2013/9/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | TMR execution on SmartCore system for dependable many-core processors |
| Sub Title (in English) | |
| Keyword(1) | Network on Chip |
| Keyword(2) | Many-core Processor |
| Keyword(3) | Triple Modular Redundancy |
| Keyword(4) | Network Performance |
| 1st Author's Name | Ryosuke SASAKAWA |
| 1st Author's Affiliation | Tokyo Institute of Technology() |
| 2nd Author's Name | Shimpei SATO |
| 2nd Author's Affiliation | Tokyo Institute of Technology |
| 3rd Author's Name | Kenji KISE |
| 3rd Author's Affiliation | Tokyo Institute of Technology |
| Date | 2013-10-03 |
| Paper # | CPSY2013-32 |
| Volume (vol) | vol.113 |
| Number (no) | 234 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |