Presentation	2013-10-03 Design of a translator to Verilog HDL from hardware modeling language ArchHDL Shimpei SATO, Kenji KISE,
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Abstract(in English)	We have proposed ArchHDL as a new language for hardware RTL modeling. In ArchHDL, we realized continuous assignment and non-blocking assignment of hardware description language by its library. Thus, users are able to describe a hardware in Verilog HDL like description. In this paper, we design a tool to translate ArchHDL code into Verilog HDL code. By this translator, ArchHDL becomes more useful tool for hardware design.
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Keyword(in English)	Hardware description language / C++ / Verilog HDL / ArchHDL
Paper #	CPSY2013-31
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Conference Information
Committee	CPSY
Conference Date	2013/9/26(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design of a translator to Verilog HDL from hardware modeling language ArchHDL
Sub Title (in English)
Keyword(1)	Hardware description language
Keyword(2)	C++
Keyword(3)	Verilog HDL
Keyword(4)	ArchHDL
1st Author's Name	Shimpei SATO
1st Author's Affiliation	Graduate School of Information Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name	Kenji KISE
2nd Author's Affiliation	Graduate School of Information Science and Engineering, Tokyo Institute of Technology
Date	2013-10-03
Paper #	CPSY2013-31
Volume (vol)	vol.113
Number (no)	234
Page	pp.pp.-
#Pages	6
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