Presentation 2013-10-24
Design of an FPGA-Based FDTD Accelerator Using OpenCL
Yasuhiro Takei, Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama,
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Abstract(in English) High-performance computing systems with dedicated hardware on FPGAs can achieve power efficient computations compared with CPUs and GPUs. However, the hardware design on FPGAs needs more time than the software design on CPUs and GPUs.We designed an FDTD hardware accelerator using the OpenCL compiler for FPGA in this paper. Since it is possible to create hardware automatically from the OpenCL code by using this compiler, we can implement applications on FPGAs in a short time compared with the design with a hardware description language.According to the result of the implementation of the FDTD accelerator on the FPGA, the processing speed is faster than CPU. Moreover, the power consumption is about one-tenth of GPU.
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Keyword(in English) OpenCL / FPGA / FDTD method / Hardware accelerator
Paper # EMCJ2013-73,MW2013-113,EST2013-65
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Committee EMCJ
Conference Date 2013/10/17(1days)
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Registration To Electromagnetic Compatibility (EMCJ)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of an FPGA-Based FDTD Accelerator Using OpenCL
Sub Title (in English)
Keyword(1) OpenCL
Keyword(2) FPGA
Keyword(3) FDTD method
Keyword(4) Hardware accelerator
1st Author's Name Yasuhiro Takei
1st Author's Affiliation Tohoku University()
2nd Author's Name Hasitha Muthumala
2nd Author's Affiliation Tohoku University
3rd Author's Name Masanori Hariyama
3rd Author's Affiliation Tohoku University
4th Author's Name Michitaka Kameyama
4th Author's Affiliation Tohoku University
Date 2013-10-24
Paper # EMCJ2013-73,MW2013-113,EST2013-65
Volume (vol) vol.113
Number (no) 259
Page pp.pp.-
#Pages 4
Date of Issue