Presentation 2013-08-02
A Full Asynchronous Nano-Watt SAR ADC by Boosted Power Gating
Ryo Saito, Ryota Sekimoto, Akira Shikata,
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Abstract(in English) This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous operation and boosted power gating are proposed to improve conversion accuracy and reduce static leakage power. Test chip fabricated in 40nm CMOS process has successfully reduced leakage power by 98% and it performs ENOB of 8.2bit and consumes only 0.65nW with 0.1kS/s at 0.5V. The power consumption is scalable up to 4MS/s and power supply range from 0.4 to 0.7V. The best figure of merit (FoM) of 5.2fJ/conversion-step was obtained with 20kS/s at 0.5V.
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Keyword(in English) Successive Approximation / Sensor Network / Scalable
Paper # SDM2013-81,ICD2013-63
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Conference Date 2013/7/25(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Full Asynchronous Nano-Watt SAR ADC by Boosted Power Gating
Sub Title (in English)
Keyword(1) Successive Approximation
Keyword(2) Sensor Network
Keyword(3) Scalable
1st Author's Name Ryo Saito
1st Author's Affiliation Graduate Course Science and Engineering, Keio University()
2nd Author's Name Ryota Sekimoto
2nd Author's Affiliation Graduate Course Science and Engineering, Keio University
3rd Author's Name Akira Shikata
3rd Author's Affiliation Graduate Course Science and Engineering, Keio University
Date 2013-08-02
Paper # SDM2013-81,ICD2013-63
Volume (vol) vol.113
Number (no) 173
Page pp.pp.-
#Pages 5
Date of Issue