講演名 2013-08-01
Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects
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抄録(和)
抄録(英) Bumpless interconnects prospected to the Tera-byte large scale integration using three-dimensional (3D) processes has been discussed. The key feature of bumpless as well as no bump interconnects is a second-generation alternative to the use of micro-bump for Wafer-on-Wafer (WOW). In our 3D interconnects technology is classified into Via-Last from the front side and stacking Back-to-Front in which any number of thinned 300 mm wafers and/or heterogeneous dies can be stacked realizing further large-scale devices with low cost rather than the use of extreme ultraviolet (EUV) lithography which will be expected at 18~22 nm and beyond. In the economic sense in many situations, WOW is the leading-edge process among 3D processes because stacking at the wafer level drastically increases the processing throughput and bumpless interconnects provide an appropriate yield using existing technology which is equivalent to or greater than that achievable with 2D scaling beyond 22 nm nodes. This paper is described by our recent studies as shown in references.
キーワード(和)
キーワード(英) Bumpless Interconnects / Tera-Scale / Chip-on-Wafer / Wafer-on-Wafer / Thinning-First / Via-last after Bonding
資料番号 SDM2013-70,ICD2013-52
発行日

研究会情報
研究会 ICD
開催期間 2013/7/25(から1日開催)
開催地(和)
開催地(英)
テーマ(和)
テーマ(英)
委員長氏名(和)
委員長氏名(英)
副委員長氏名(和)
副委員長氏名(英)
幹事氏名(和)
幹事氏名(英)
幹事補佐氏名(和)
幹事補佐氏名(英)

講演論文情報詳細
申込み研究会 Integrated Circuits and Devices (ICD)
本文の言語 ENG
タイトル(和)
サブタイトル(和)
タイトル(英) Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects
サブタイトル(和)
キーワード(1)(和/英) / Bumpless Interconnects
第 1 著者 氏名(和/英) / Takayuki OHBA
第 1 著者 所属(和/英)
Information, Communication and Energy (ICE Cube Center)
発表年月日 2013-08-01
資料番号 SDM2013-70,ICD2013-52
巻番号(vol) vol.113
号番号(no) 173
ページ範囲 pp.-
ページ数 2
発行日