| Presentation | 2013-08-02 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko UMEMOTO, Koji NII, Jiro ISHIKAWA, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Shinji TANAKA, Koji TANAKA, Kazutaka MORI, Kazumasa YANAGISAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent highspeed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 28nm / CMOS / Memory / Embedded ROM / 2T ROM bitcell / High speed / Low power source bias control |
| Paper # | SDM2013-77,ICD2013-59 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2013/7/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique |
| Sub Title (in English) | |
| Keyword(1) | 28nm |
| Keyword(2) | CMOS |
| Keyword(3) | Memory |
| Keyword(4) | Embedded ROM |
| Keyword(5) | 2T ROM bitcell |
| Keyword(6) | High speed |
| Keyword(7) | Low power source bias control |
| 1st Author's Name | Yukiko UMEMOTO |
| 1st Author's Affiliation | Renesas Electronics Corporation() |
| 2nd Author's Name | Koji NII |
| 2nd Author's Affiliation | Renesas Electronics Corporation |
| 3rd Author's Name | Jiro ISHIKAWA |
| 3rd Author's Affiliation | Renesas Electronics Corporation |
| 4th Author's Name | Makoto YABUUCHI |
| 4th Author's Affiliation | Renesas Electronics Corporation |
| 5th Author's Name | Yasumasa TSUKAMOTO |
| 5th Author's Affiliation | Renesas Electronics Corporation |
| 6th Author's Name | Shinji TANAKA |
| 6th Author's Affiliation | Renesas Electronics Corporation |
| 7th Author's Name | Koji TANAKA |
| 7th Author's Affiliation | Renesas Electronics Corporation |
| 8th Author's Name | Kazutaka MORI |
| 8th Author's Affiliation | Renesas Electronics Corporation |
| 9th Author's Name | Kazumasa YANAGISAWA |
| 9th Author's Affiliation | Renesas Electronics Corporation |
| Date | 2013-08-02 |
| Paper # | SDM2013-77,ICD2013-59 |
| Volume (vol) | vol.113 |
| Number (no) | 172 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |