| Presentation | 2013-09-19 Development of Memory Management Framework for FPGA-based Prototyping Shinya TAKAMAEDA-YAMAZAKI, Kenji KISE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | FPGA-based rapid prototyping supports faster emulation, but it requires the detailed implementation for each FPGA characteristic, especially memory resources. It makes it harder to implement a sufficient memory system of the target architecture on FPGA. In this paper, we propose a new framework to automatically synthesize a specialized memory system for FPGA-based rapid prototyping. The framework provides an abstracted fast memory via a simple interface by employing on-chip memory fabrics and off-chip large-capacity memory components. We evaluated our framework on an actual FPGA system, by using an advanced multicore architecture as a target of prototyping. The evaluation result shows that the multicore designed with an assumption of infinite on-chip memory on FPGA can be emulated at realistic speed with keeping the cycle-accuracy, by using the synthesized memory system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Prototyping / Cycle-Accurate Emulation / Memory System |
| Paper # | RECONF2013-35 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Memory Management Framework for FPGA-based Prototyping |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Prototyping |
| Keyword(3) | Cycle-Accurate Emulation |
| Keyword(4) | Memory System |
| 1st Author's Name | Shinya TAKAMAEDA-YAMAZAKI |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology:JSPS Research Fellow (DC1)() |
| 2nd Author's Name | Kenji KISE |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering Tokyo Institute of Technology |
| Date | 2013-09-19 |
| Paper # | RECONF2013-35 |
| Volume (vol) | vol.113 |
| Number (no) | 221 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |