Presentation 2013-09-19
A Packet Classifier using Parallel EVMDD (k) Machine
Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA,
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Abstract(in English) A decision diagram machine(DDM) is a special-purpose processor that uses special instructions to evaluate a decision diagram. Thus, the architecture for the DDM is much simpler than that for a general-purpose microprocessor(MPU).Since the DDM uses the dedicated instructions for a special-purpose application, it is faster than the MPU. This paper presents a packet classifier using a parallel EVMDD(k) machine. To reduce computation time and code size, first, a set of rules for packet classifier is partitioned into groups. Then, the parallel EVMDD(k) machine evaluates them. We implemented the parallel EVMDD(k) machine consisting of 32 EVMDD(4) machines on an FPGA, and compared it with the Intel's Core i5 microprocessor running at 1.7GHz.It is 7.8-40.1 times faster than the Core i5, and it requires only 12.0-52.6 percents of the memory for the Core i5.
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Paper # RECONF2013-34
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Committee RECONF
Conference Date 2013/9/11(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
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Title (in English) A Packet Classifier using Parallel EVMDD (k) Machine
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1st Author's Name Hiroki NAKAHARA
1st Author's Affiliation Faculty of Engineering, Kagoshima University()
2nd Author's Name Tsutomu SASAO
2nd Author's Affiliation Department of Computer Science, Meiji University
3rd Author's Name Munehiro MATSUURA
3rd Author's Affiliation Department of Computer Science, Kyushu Institute of Technology
Date 2013-09-19
Paper # RECONF2013-34
Volume (vol) vol.113
Number (no) 221
Page pp.pp.-
#Pages 6
Date of Issue