Presentation 2013-09-19
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems
Koichi ARAKI, Yukinori SATO, Yasushi INOGUCHI,
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Abstract(in English) Abstract In this paper, we propose a low power oriented design framework for Embedded Systems. Our frame-work automatically performs an optimization to satisfy response time constrain, which relates to reconfiguration time, and throughput constrain. In case study, we show that hardware ,which is 1D-IDCT in MPEG2 targeting HDTV, from our framework satisfies those constrain. Also, our proposed framework significantly reduces line of codes although power consumption of hardware from it is slightly higher than that of hardware manually tuned using a high-level synthesis and HDLs.
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Keyword(in English) Embedded System / FPGA / Hardware Design
Paper # RECONF2013-31
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Committee RECONF
Conference Date 2013/9/11(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems
Sub Title (in English)
Keyword(1) Embedded System
Keyword(2) FPGA
Keyword(3) Hardware Design
1st Author's Name Koichi ARAKI
1st Author's Affiliation Center for Highly Dependable Embedded Systems Technology, Japan Advanced Institute of Science and Technology()
2nd Author's Name Yukinori SATO
2nd Author's Affiliation Research Center for Advanced Computing Infrastructure, Japan Advanced Institute of Science and Technology
3rd Author's Name Yasushi INOGUCHI
3rd Author's Affiliation Research Center for Advanced Computing Infrastructure, Japan Advanced Institute of Science and Technology
Date 2013-09-19
Paper # RECONF2013-31
Volume (vol) vol.113
Number (no) 221
Page pp.pp.-
#Pages 6
Date of Issue