| Presentation | 2013-09-19 A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique Hongliang SU, Weihan WANG, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Leakage power is a serious problem especially for accerelators which use a large size Processing Element (PE) array. Here, a low power reconfigurable accelerator called Cool Mega Array (CMA) with back-gate bias control (CMA-bb) is implemented and evaluated. In CMA-bb, the back-gate bias of the microcontroller and PE array can be controlled independently. In the idle mode, reverse bias is given to the both parts to suppress the leakage current. When high performance is required, forward bias is used to increase the clock frequency. For simple applications, the operational power can be suppressed by using reverse bias only in the PE array. On the other hand, by giving forward bias to the PE array, the performance can be increased with a small increases of the power in the computation centric applications. The real chip is implemented with a 65nm experimental process for low leakage applications. The evaluation results show that the leakage current can be suppressed to 300μA by using the reverse bias. The operational frequency is increased from 39MHz to 50MHz with up to 21% increase of operational power by using the forward bias. For simple applications, 8% to 9.4% of operational power is saved by giving reverse bias only to the PE array. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Corase Grained Reconfigurable Processor / Leakage Power Reduction / Back-gate Bias Control |
| Paper # | RECONF2013-26 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique |
| Sub Title (in English) | |
| Keyword(1) | Corase Grained Reconfigurable Processor |
| Keyword(2) | Leakage Power Reduction |
| Keyword(3) | Back-gate Bias Control |
| 1st Author's Name | Hongliang SU |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Weihan WANG |
| 2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 3rd Author's Name | Hideharu AMANO |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2013-09-19 |
| Paper # | RECONF2013-26 |
| Volume (vol) | vol.113 |
| Number (no) | 221 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |