| Presentation | 2013-09-18 A Power-Performance model for 3-D stencil computation on an FPGA accelerator Keisuke DOHI, Kota FUKUMOTO, Yuichiro SHIBATA, Kiyoshi OGURI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents user space parameters and characteristics modeling of 3-D stencil computing on a stream-oriented FPGA accelerator. We adopted a heat conduction simulation as a benchmark. The benchmark was developed with high-level synthesis tools, Max Compiler and Max Gen FD, which are domain specific frameworks for finite-difference equations. The fastest FPGA design achieved six times speedup from SIMD-enabled and multi-threaded CPU-based design. Energy comsumptions of the FPGA accelerator were measured and the best configuration in terms of performance also shows the lowest energy consumption. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | RECONF2013-23 |
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| Committee | RECONF |
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| Conference Date | 2013/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power-Performance model for 3-D stencil computation on an FPGA accelerator |
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| 1st Author's Name | Keisuke DOHI |
| 1st Author's Affiliation | Graduate School of Engineering, Nagasaki University() |
| 2nd Author's Name | Kota FUKUMOTO |
| 2nd Author's Affiliation | Graduate School of Engineering, Nagasaki University |
| 3rd Author's Name | Yuichiro SHIBATA |
| 3rd Author's Affiliation | Graduate School of Engineering, Nagasaki University |
| 4th Author's Name | Kiyoshi OGURI |
| 4th Author's Affiliation | Graduate School of Engineering, Nagasaki University |
| Date | 2013-09-18 |
| Paper # | RECONF2013-23 |
| Volume (vol) | vol.113 |
| Number (no) | 221 |
| Page | pp.pp.- |
| #Pages | 6 |
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