Presentation 2013-06-21
An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Kentaroh Katoh,
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Abstract(in English) This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The proposed online test architecture consists of functional cores with boundary scan design and a relative small-sized embedded reconfigurable core. The extra area of the proposed online is smaller than conventional self-checking circuits or hardware redundancy approaches. Unlike conventional online BIST approach, the proposed online test does not hinder the functional operation. Therefore it is suitable to the chips for real-time applications. The experiments with ISCAS 89 benchmarks reveal that the error latency 4.3 (ms). The time-multiplexed test strategy reduces 24 % the area of the embedded reconfigurable core.
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Keyword(in English) SOC / online interconnect test / boundary scan / embedded reconfigurable core
Paper # DC2013-14
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Committee DC
Conference Date 2013/6/14(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Sub Title (in English)
Keyword(1) SOC
Keyword(2) online interconnect test
Keyword(3) boundary scan
Keyword(4) embedded reconfigurable core
1st Author's Name Kentaroh Katoh
1st Author's Affiliation Dept. of Electrical Engineering, Tsuruoka National College of Technology()
Date 2013-06-21
Paper # DC2013-14
Volume (vol) vol.113
Number (no) 104
Page pp.pp.-
#Pages 5
Date of Issue