Presentation 2013-06-21
A method of deterministic LFSR Seed Generation for Scan-Based BIST
Takanori MORIYASU, Satoshi OHTAKE,
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Abstract(in English) This paper proposes a method of LFSR seed generation for LFSR reseeding of scan-based BIST of VLSI circuits. So far, a scan test pattern detecting some fault is first generated using an ATPG tool and the generated pattern is then converted into a seed. However, the conversion does not always succeed and the fault may not be detected. For a given circuit with scan-based BIST, the proposed method first creates a seed generation model for the circuit. The seed generation model consists of the combinational part of the circuit and the XOR network representing the logic functions of LFSR seed variables for scan flip-flops. LFSR seeds for faults are then generated as test patterns of the seed generation model by using an ATPG tool. In this paper, the effectiveness of the proposed method is shown by experiments using ITC'99 benchmark circuits.
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Keyword(in English) Scan-based BIST / LFSR / reseeding / seed generation / test generation constraint
Paper # DC2013-11
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Committee DC
Conference Date 2013/6/14(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A method of deterministic LFSR Seed Generation for Scan-Based BIST
Sub Title (in English)
Keyword(1) Scan-based BIST
Keyword(2) LFSR
Keyword(3) reseeding
Keyword(4) seed generation
Keyword(5) test generation constraint
1st Author's Name Takanori MORIYASU
1st Author's Affiliation Graduate School of Engineering, Oita University()
2nd Author's Name Satoshi OHTAKE
2nd Author's Affiliation Faculty of Engineering, Oita University:CREST, Japan Science and Technology Agency
Date 2013-06-21
Paper # DC2013-11
Volume (vol) vol.113
Number (no) 104
Page pp.pp.-
#Pages 6
Date of Issue