Presentation 2013-06-21
A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke KODAMA, Jun NISHIMAKI, Tetuya MASUDA, Toshinori HOSOKAWA, Hideo FUJIWARA,
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Abstract(in English) In recent years, various high-level test synthesis methods for Las have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches are to separate a controller and a data path by using scan design, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually degrades the testability. To resolve this problem, an approach that augments a controller by adding extra control functions to make a data path easily testable was proposed However, the approach cannot always succeed in generating test sequences with high fault coverage if a general ATPG tool is used without knowing any information of augmented control functions. In this paper, we introduce "easily testable functional k-time expansion models for data paths" and propose a method for augmenting a controller such that easily testable functional k-time expansion models for the data path are generated. Experimental results show the effectiveness of the proposed method.
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Keyword(in English) non-scan testing / easily testable functional k-time expansion models / controller augmentation / sequential test generation
Paper # DC2013-10
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Committee DC
Conference Date 2013/6/14(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Sub Title (in English)
Keyword(1) non-scan testing
Keyword(2) easily testable functional k-time expansion models
Keyword(3) controller augmentation
Keyword(4) sequential test generation
1st Author's Name Yusuke KODAMA
1st Author's Affiliation Graduate School of Industrial Technology, Nihon University()
2nd Author's Name Jun NISHIMAKI
2nd Author's Affiliation Graduate School of Industrial Technology, Nihon University
3rd Author's Name Tetuya MASUDA
3rd Author's Affiliation College of Industrial Technology, Nihon University
4th Author's Name Toshinori HOSOKAWA
4th Author's Affiliation College of Industrial Technology, Nihon University
5th Author's Name Hideo FUJIWARA
5th Author's Affiliation Faculty of Informatics, Osaka Gakuin University
Date 2013-06-21
Paper # DC2013-10
Volume (vol) vol.113
Number (no) 104
Page pp.pp.-
#Pages 6
Date of Issue