Presentation 2013-07-04
Fabrication of Stacked Logic Circuits for Printed Integrated Circuits
Kazuhiro KUDO, Isao KODERA, Hiroshi YAMAUCHI, Shigekazu KUNIYOSHI, Masatoshi SAKAI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have demonstrated logic circuit operations of stacked-structure thin film transistor (TFT) circuits using TIPS-pentacene (6,13-Bis(triisopropylsilylethynyl)pentacene) and soluble ZnO as active layers. Bottom-gate-type TIPS-pentacene TFTs, as p-channel transistors, were formed on top-gate-type ZnO TFTs with common gate electrodes. For both TFTs, solution-processed silicone-resin layers were used as gate dielectric. The stacked-structure TFT circuit has several advantages such as easiness of active material patterning, compact device area per stage, and the short length of the interconnection as compared with the planar configuration in a conventional logic circuit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Stacked Structure TFT / Logic Circuit / Silicone-resin / TIPS-pentacene / ZnO
Paper # OME2013-47
Date of Issue

Conference Information
Committee OME
Conference Date 2013/6/27(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Organic Material Electronics (OME)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fabrication of Stacked Logic Circuits for Printed Integrated Circuits
Sub Title (in English)
Keyword(1) Stacked Structure TFT
Keyword(2) Logic Circuit
Keyword(3) Silicone-resin
Keyword(4) TIPS-pentacene
Keyword(5) ZnO
1st Author's Name Kazuhiro KUDO
1st Author's Affiliation Graduate School of Engineering, Chiba University()
2nd Author's Name Isao KODERA
2nd Author's Affiliation Graduate School of Engineering, Chiba University
3rd Author's Name Hiroshi YAMAUCHI
3rd Author's Affiliation Graduate School of Engineering, Chiba University
4th Author's Name Shigekazu KUNIYOSHI
4th Author's Affiliation Graduate School of Engineering, Chiba University
5th Author's Name Masatoshi SAKAI
5th Author's Affiliation Graduate School of Engineering, Chiba University
Date 2013-07-04
Paper # OME2013-47
Volume (vol) vol.113
Number (no) 115
Page pp.pp.-
#Pages 6
Date of Issue