Presentation 2013-07-05
1-GHz, 8-bit Subranging ADC(1) : Low-power techniques
Masataro IWAMOTO, Wataru YOSHIMURA, Futoshi SHIMOZONO, Daiki TABIRA, Kenichi OHHATA,
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Abstract(in English) An AD converter architecture combining a capacitive DAC and a built-in Vth technology was proposed to reduce the power consumption in high-speed subranging ADCs. Moreover, a calibration technique comprising of MOM capacitor, MOS switch and scaling capacitor and the offset drift compensation technique were proposed to reduce the power consumption of the comparator. We designed an 8-bit, 1-GHz subranging AD converter applying these techniques and post-layout simulation results demonstrated the power consumption of 7 mW and FOM of 51 fJ/conv.-step.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) AD converter / Subranging / Foreground calibration / Drift compensation
Paper # ICD2013-40
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Committee ICD
Conference Date 2013/6/27(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 1-GHz, 8-bit Subranging ADC(1) : Low-power techniques
Sub Title (in English)
Keyword(1) AD converter
Keyword(2) Subranging
Keyword(3) Foreground calibration
Keyword(4) Drift compensation
1st Author's Name Masataro IWAMOTO
1st Author's Affiliation Dept. of Electrical and Electronics Engineering, Kagoshima University()
2nd Author's Name Wataru YOSHIMURA
2nd Author's Affiliation Dept. of Electrical and Electronics Engineering, Kagoshima University
3rd Author's Name Futoshi SHIMOZONO
3rd Author's Affiliation Dept. of Electrical and Electronics Engineering, Kagoshima University
4th Author's Name Daiki TABIRA
4th Author's Affiliation Dept. of Electrical and Electronics Engineering, Kagoshima University
5th Author's Name Kenichi OHHATA
5th Author's Affiliation Dept. of Electrical and Electronics Engineering, Kagoshima University
Date 2013-07-05
Paper # ICD2013-40
Volume (vol) vol.113
Number (no) 112
Page pp.pp.-
#Pages 6
Date of Issue