| Presentation | 2013-07-11 Design Method of On-Board RL Snubber Inserted in Power Distribution Network of Integrated Circuits Ryosuke YAMAGATA, Kengo IOKIBE, Yoshitaka TOYOTA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The power distribution network (PDN) of modern integrated circuits (ICs) have parasitic impedances along power and ground traces, vias, and components as well as nominal impedances of the components: capacitors, voltage regulators, filters, and ICs. Such parasitic impedances, at the resonant frequency, may increase the radio frequency (RF) power current to cause conducted EM radiation and surge the PDN input impedance to induce power bounces. There is the RL snubber circuit that had been applied to a typical PDN decreasing the RF power current and descending the PDN input impedance by damping the parasitic impedance resonance. The RL snubber is composed of a parallel pair of decoupling inductor and damping resister. This report introduced a design method of the RL snubber for the parasitic impedance resonance of on-board parasitic capacitances.In the design method, the allowable range of the decoupling inductance was restricted for practical use of the method to simplify the equivalent circuit that expressed the target resonance. The simplified equivalent circuit was a 2nd order circuit whereas the original one was 3rd order.With the restricted inductance, an optimal resistance was determined in accordance with the critical damping conditions of the 2nd order circuit. Finally, the design method was evaluated on the basis of the circuit simulation calculating the current transmittance and PDN input impedance. As a result, the introduced design method was confirmed to reduce as much RF power current and power bounce as the more thetically strict way. Moreover, the method was found to be able to be more practical by relaxing the restriction on the decoupling inductance of RL snubber. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | EMC / IC / Power Distribution Network / Damping Resister / Power Integnity |
| Paper # | EMCJ2013-34 |
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| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2013/7/4(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Electromagnetic Compatibility (EMCJ) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Method of On-Board RL Snubber Inserted in Power Distribution Network of Integrated Circuits |
| Sub Title (in English) | |
| Keyword(1) | EMC |
| Keyword(2) | IC |
| Keyword(3) | Power Distribution Network |
| Keyword(4) | Damping Resister |
| Keyword(5) | Power Integnity |
| 1st Author's Name | Ryosuke YAMAGATA |
| 1st Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University() |
| 2nd Author's Name | Kengo IOKIBE |
| 2nd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 3rd Author's Name | Yoshitaka TOYOTA |
| 3rd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| Date | 2013-07-11 |
| Paper # | EMCJ2013-34 |
| Volume (vol) | vol.113 |
| Number (no) | 122 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |