Presentation 2013-07-11
Impedance Balance Control for Suppression of Substrate Noise Coupling in CMOS IC
Masaaki MAEDA, Tohlu MATSUSHIMA, Takashi HISAKADO, Osami WADA,
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Abstract(in English) Simultaneous switching current generated by operation of a CMOS circuit is injected into the CMOS substrate, and causes the substrate voltage bounce. The performance of the circuit degrades due to the voltage bounce. In this report, we focus on the fact that parasitic couplings in the CMOS substrate and parasitic inductance in the power and ground connection form a bridge circuit, and we demonstrate that the voltage bounce can be suppressed by controlling variable resistances that are inserted between the substrate resistive coupling and the conductor line for the power supply. The effectiveness of this method is verified with a quad flat package (QFP) and we reduced the voltage bounce about 40 dB.
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Keyword(in English) CMOS circuit / Substrate noise coupling / Impedance balance control / QFP
Paper # EMCJ2013-30
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Committee EMCJ
Conference Date 2013/7/4(1days)
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Registration To Electromagnetic Compatibility (EMCJ)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Impedance Balance Control for Suppression of Substrate Noise Coupling in CMOS IC
Sub Title (in English)
Keyword(1) CMOS circuit
Keyword(2) Substrate noise coupling
Keyword(3) Impedance balance control
Keyword(4) QFP
1st Author's Name Masaaki MAEDA
1st Author's Affiliation Department of Electrical Engineering, Kyoto University()
2nd Author's Name Tohlu MATSUSHIMA
2nd Author's Affiliation Department of Electrical Engineering, Kyoto University
3rd Author's Name Takashi HISAKADO
3rd Author's Affiliation Department of Electrical Engineering, Kyoto University
4th Author's Name Osami WADA
4th Author's Affiliation Department of Electrical Engineering, Kyoto University
Date 2013-07-11
Paper # EMCJ2013-30
Volume (vol) vol.113
Number (no) 122
Page pp.pp.-
#Pages 6
Date of Issue