Presentation 2013-07-22
Design and Evaluation of the 2-bit Bit-Slice Adder Based on 10kA/cm^2 Process
Kensuke TAKATA, Yuhi HAYAKAWA, Masamitsu TANAKA, Akira FUJIMAKI,
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Abstract(in English) A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.
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Keyword(in English) SFQ circuit / 10 kA/cm^2 process / 2-bit bit-slice adder
Paper # SCE2013-12
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Committee SCE
Conference Date 2013/7/15(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Evaluation of the 2-bit Bit-Slice Adder Based on 10kA/cm^2 Process
Sub Title (in English)
Keyword(1) SFQ circuit
Keyword(2) 10 kA/cm^2 process
Keyword(3) 2-bit bit-slice adder
1st Author's Name Kensuke TAKATA
1st Author's Affiliation Department of Quantum Engineering, Nagoya University()
2nd Author's Name Yuhi HAYAKAWA
2nd Author's Affiliation Department of Quantum Engineering, Nagoya University
3rd Author's Name Masamitsu TANAKA
3rd Author's Affiliation Department of Quantum Engineering, Nagoya University
4th Author's Name Akira FUJIMAKI
4th Author's Affiliation Department of Quantum Engineering, Nagoya University
Date 2013-07-22
Paper # SCE2013-12
Volume (vol) vol.113
Number (no) 149
Page pp.pp.-
#Pages 6
Date of Issue