| Presentation | 2013-07-22 Optimization Considering Dependence of Signal Propagation Time of SFQ Logic Gates on Bias Voltage Mikio OTSUBO, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz with low power consumption. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, increasing a critical current of Josephson junction and adding bias feeding line in the SFQ circuit control the dependence of the signal propagation time on bias voltage, that decreases a timing error and enables a wide operating margin at a high operating frequency. In this paper, we simulate the optimization of the logic circuits by controlling dependence of signal propagation time on bias voltage. The logic gates have been optimized taking the dependence of the propagation time on the bias voltage into account. Designed logic cells have larger controllability of their delay times without deterioration of the bias margins compared to the conventional logic cells. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Single flux quantum circuits / Logic gates / Timing error |
| Paper # | SCE2013-10 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2013/7/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization Considering Dependence of Signal Propagation Time of SFQ Logic Gates on Bias Voltage |
| Sub Title (in English) | |
| Keyword(1) | Single flux quantum circuits |
| Keyword(2) | Logic gates |
| Keyword(3) | Timing error |
| 1st Author's Name | Mikio OTSUBO |
| 1st Author's Affiliation | Yokohama National University() |
| 2nd Author's Name | Yuki YAMANASHI |
| 2nd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 3rd Author's Name | Nobuyuki YOSHIKAWA |
| 3rd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| Date | 2013-07-22 |
| Paper # | SCE2013-10 |
| Volume (vol) | vol.113 |
| Number (no) | 149 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |