| Presentation | 2013-07-12 Low Power Memory Based Design Method of Constant Multipliers for Digital Filters Kosuke KABASAWA, Tadahiko SUGIBAYASHI, Masao YANAGISAWA, Shinji KIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Digital Signal Processing of sounds and images are using many digital filters which computes the summation of multiplications between a sequence of constants and a time sequence of an input. In this manuscript, a memory based design method for such constant multiplication is described. In the design, the trade-off between the size of a memory and that of the logic is considered, and its speed and power consumption is optimized. The read power of a memory is independent with the output read from the memory and a memory can encapsulate the toggles of logic gates in gate-based designs. By separating an input into several parts and designing such separated small multipliers using a memory, the memory size can be reduced drastically. The proposed constant multiplier has been implemented on ASIC, and shows the power reduction compared with gate-level design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Memory-Based Design / Digital Filter / IIR Filter / FIR Filter / Input Separation for Multiplier |
| Paper # | CAS2013-19,VLD2013-29,SIP2013-49,MSS2013-19 |
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| Conference Information | |
| Committee | MSS |
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| Conference Date | 2013/7/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Mathematical Systems Science and its applications(MSS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low Power Memory Based Design Method of Constant Multipliers for Digital Filters |
| Sub Title (in English) | |
| Keyword(1) | Memory-Based Design |
| Keyword(2) | Digital Filter |
| Keyword(3) | IIR Filter |
| Keyword(4) | FIR Filter |
| Keyword(5) | Input Separation for Multiplier |
| 1st Author's Name | Kosuke KABASAWA |
| 1st Author's Affiliation | Faculty of Science and Engineering, Waseda University() |
| 2nd Author's Name | Tadahiko SUGIBAYASHI |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Faculty of Science and Engineering, Waseda University |
| 4th Author's Name | Shinji KIMURA |
| 4th Author's Affiliation | Faculty of Science and Engineering, Waseda University |
| Date | 2013-07-12 |
| Paper # | CAS2013-19,VLD2013-29,SIP2013-49,MSS2013-19 |
| Volume (vol) | vol.113 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |