Presentation 2013-07-12
Evaluation of energy consumption for two-level cache using Non-Volatile Memory for IL1 and UL2 caches
Shota MATSUNO, Masashi TAWADA, Masao YANAGISAWA, Shinji KIMURA, Nozomu TOGAWA, Tadahiko SUGIBAYASHI,
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Abstract(in English) A non-volatile memory has advantages such as low leak energy and non-volatility compared with SRAM or DRAM has high leak energy. It is strongly expected to use a non-volatile memory for realizing normally-off systems. A non-volatile memory, however, consumes more energy to write than SRAM or DRAM. In this paper, we evaluate energy consumption of a cache memory in an embedded processor with non-volatile memories. In our evaluation, we assume that their write energy is 1.0x to 10.0x higher than that of SRAM. Experimental evaluations demonstrate that using non-volatile memories in a cache is better choice in some cases, even when write energy of non-volatile memories is 10.0x higher than that of SRAM.
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Paper # CAS2013-17,VLD2013-27,SIP2013-47,MSS2013-17
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Conference Date 2013/7/4(1days)
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Language JPN
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Title (in English) Evaluation of energy consumption for two-level cache using Non-Volatile Memory for IL1 and UL2 caches
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1st Author's Name Shota MATSUNO
1st Author's Affiliation Waseda University()
2nd Author's Name Masashi TAWADA
2nd Author's Affiliation Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Waseda University
4th Author's Name Shinji KIMURA
4th Author's Affiliation Waseda University
5th Author's Name Nozomu TOGAWA
5th Author's Affiliation Waseda University
6th Author's Name Tadahiko SUGIBAYASHI
6th Author's Affiliation NEC Corporation
Date 2013-07-12
Paper # CAS2013-17,VLD2013-27,SIP2013-47,MSS2013-17
Volume (vol) vol.113
Number (no) 121
Page pp.pp.-
#Pages 6
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