Presentation	2013-07-11 An Area and Delay Efficient Implementation of The Index Generation Functions Yusuke MATSUNAGA,
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Abstract(in English)	The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a new method implementing the index generation functions, which requires only one memory access while the existing method requires twice. The proposed method also has an advantage for total memory size against to the existing method.
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Keyword(in English)	index generation function / logic synthesis
Paper #	CAS2013-15,VLD2013-25,SIP2013-45,MSS2013-15
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Conference Information
Committee	MSS
Conference Date	2013/7/4(1days)
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Paper Information
Registration To	Mathematical Systems Science and its applications(MSS)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	An Area and Delay Efficient Implementation of The Index Generation Functions
Sub Title (in English)
Keyword(1)	index generation function
Keyword(2)	logic synthesis
1st Author's Name	Yusuke MATSUNAGA
1st Author's Affiliation	Faculty of Information Science and Electorical Engineering, Kyushu University()
Date	2013-07-11
Paper #	CAS2013-15,VLD2013-25,SIP2013-45,MSS2013-15
Volume (vol)	vol.113
Number (no)	121
Page	pp.pp.-
#Pages	6
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