| Presentation | 2013-04-12 A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara, Takayasu Sakurai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | 1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SRAM / Hierarchical Bit Line / Non-Selected Column / Charge Share |
| Paper # | ICD2013-20 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2013/4/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | Hierarchical Bit Line |
| Keyword(3) | Non-Selected Column |
| Keyword(4) | Charge Share |
| 1st Author's Name | Shinichi Moriwaki |
| 1st Author's Affiliation | Semiconductor Technology Academic Research Center(STARC)() |
| 2nd Author's Name | Yasue Yamamoto |
| 2nd Author's Affiliation | Semiconductor Technology Academic Research Center(STARC) |
| 3rd Author's Name | Toshikazu Suzuki |
| 3rd Author's Affiliation | Semiconductor Technology Academic Research Center(STARC) |
| 4th Author's Name | Atsushi Kawasumi |
| 4th Author's Affiliation | Toshiba Corporation |
| 5th Author's Name | Shinji Miyano |
| 5th Author's Affiliation | Semiconductor Technology Academic Research Center(STARC) |
| 6th Author's Name | Hirofumi Shinohara |
| 6th Author's Affiliation | Semiconductor Technology Academic Research Center(STARC) |
| 7th Author's Name | Takayasu Sakurai |
| 7th Author's Affiliation | The University of Tokyo |
| Date | 2013-04-12 |
| Paper # | ICD2013-20 |
| Volume (vol) | vol.113 |
| Number (no) | 1 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |