| Presentation | 2013-05-17 Evaluation of 3D on-chip network structures suitable to a data center Takahide IKEDA, Yuichi OHSITA, Masayuki MURATA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In a data center, servers cooperate with each other to handle a large amount of data. As the size of data increases, the energy consumption of the data center increases. To reduce the energy consumption of the data center, an architecture called on-chip data center has been proposed. In this architecture, a large number of CPUs are deployed on a single chip and connected by using Network on Chip (NoC). In this paper, we focus on the 3-D network-on-chip, which reduce the energy consumption compared with 2-D network-on-chip. Then, we deploy packet switches and circuit switches, to accommodate the traffic between servers on the chip efficiently. In this paper, we discuss the network structure by the following points; (1) connection between switches of different layers, (2) the layer of the switches connected to servers, and (3) the arrangement of switches on each layer. We evaluate the energy consumption and the latency between servers. The result clarifies that to reduce the energy consumption and the latency, (1) switches on all layers should be connected to the switch on a certain layer, (2) all servers should connect to the switch on the same layer, and (3) all switches on each layer should be the same kind of switch. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NoC / data center / power consumption / latency / 3D on-chip network |
| Paper # | IN2013-20 |
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| Conference Information | |
| Committee | IN |
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| Conference Date | 2013/5/9(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Networks (IN) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of 3D on-chip network structures suitable to a data center |
| Sub Title (in English) | |
| Keyword(1) | NoC |
| Keyword(2) | data center |
| Keyword(3) | power consumption |
| Keyword(4) | latency |
| Keyword(5) | 3D on-chip network |
| 1st Author's Name | Takahide IKEDA |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Yuichi OHSITA |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Masayuki MURATA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2013-05-17 |
| Paper # | IN2013-20 |
| Volume (vol) | vol.113 |
| Number (no) | 36 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |