Presentation 2013-05-20
Speed-up of Dynamically Reconfigurable Processor Array
Toru KATAGIRI, Hideharu AMANO,
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Abstract(in English) In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increase the number of Processing Element (PE). However, since the utilization of PEs is limited depending on the parallelism on applications, increasing PE array size often does not contribute to the performance improvement. As an alternative approach, we tried a method to improve performance by speeding up PE itself rather than increasing the number of PE. First, the network of PE array is changed so as to speed up the pipelined PE. Then, the SIMD mechanism is introduced to solve data dependence produced by the pipelined PEs. As a result, the amount of hardware is reduced about 20%, the performance is improved 6.5 times, and the energy consumption is reduced by 5~28%.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dynamically Reconfigurable Processor / Accelerator / Speed-up
Paper # RECONF2013-5
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Committee RECONF
Conference Date 2013/5/13(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Speed-up of Dynamically Reconfigurable Processor Array
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) Accelerator
Keyword(3) Speed-up
1st Author's Name Toru KATAGIRI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Hideharu AMANO
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2013-05-20
Paper # RECONF2013-5
Volume (vol) vol.113
Number (no) 52
Page pp.pp.-
#Pages 6
Date of Issue