| Presentation | 2013-05-20 An FPGA Implementation of the Progressive Tree Neighborhood Algorithm : Phylogenetic Tree Reconstruction with Maximum Parsimony Henry Block, Tsutomu Maruyama, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present an FPGA-hardware implementation for the progressive tree neighborhood algorithm applied to phylogenetic tree reconstruction with maximum parsimony. The proposed hardware architecture is modular, and has pipelined stages to improve the performance and reduce the execution time of the algorithm. Implementation results for a specific problem showed a 1247x acceleration compared to a C++ software implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Bioinformatics / Maximum Parsimony / Progressive Tree Neighborhood / Hardware Acceleration / FPGA |
| Paper # | RECONF2013-2 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/5/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of the Progressive Tree Neighborhood Algorithm : Phylogenetic Tree Reconstruction with Maximum Parsimony |
| Sub Title (in English) | |
| Keyword(1) | Bioinformatics |
| Keyword(2) | Maximum Parsimony |
| Keyword(3) | Progressive Tree Neighborhood |
| Keyword(4) | Hardware Acceleration |
| Keyword(5) | FPGA |
| 1st Author's Name | Henry Block |
| 1st Author's Affiliation | () |
| 2nd Author's Name | Tsutomu Maruyama |
| 2nd Author's Affiliation | |
| Date | 2013-05-20 |
| Paper # | RECONF2013-2 |
| Volume (vol) | vol.113 |
| Number (no) | 52 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |