Presentation	2013-05-20 Challenging Connect6 Hardware Design Competitions Kentaro SANO,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	This paper describes an algorithm, an architecture, and implementation of our Connect6 hardware solver, called Nexus6-mk3, to be used in several design competition series. Nexus6-mk3 is based on our proposed two-level move refinement method and the alpha-beta pruning method to reduce time of depth-first search by the mini-Max algorithm. The hardware accelerator on FPGA achieves about 80000 and 640 times faster processing than an NIOS II processor at 110MHz on FPGA and a single core of Intel Core i7 processor running at 2.93 GHz, respectively. The solution with a very cheap and low-power FPGA demonstrates that the FPGA-based solver is advantageous not only for processing performance, but also performance per cost and performance per power.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Connect6 solver / FPGA / hardware accelerator / game-tree search
Paper #	RECONF2013-1
Date of Issue

Conference Information
Committee	RECONF
Conference Date	2013/5/13(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Challenging Connect6 Hardware Design Competitions
Sub Title (in English)
Keyword(1)	Connect6 solver
Keyword(2)	FPGA
Keyword(3)	hardware accelerator
Keyword(4)	game-tree search
1st Author's Name	Kentaro SANO
1st Author's Affiliation	Graduate School of Information Sciences, Tohoku University()
Date	2013-05-20
Paper #	RECONF2013-1
Volume (vol)	vol.113
Number (no)	52
Page	pp.pp.-
#Pages	6
Date of Issue