| Presentation | 2013-04-26 A low latency topology for NoC using multiple host links Ryuta KAWANO, Ikki FUJIWARA, Hiroki MATSUTANI, Hideharu AMANO, Michihiro KOIBUCHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent many-core architectures, the number of cores has been steadily increasing. Therefore, network latency between cores has become a more important issue for applications. Because packet network structures (Network-on-Chip, NoC) are widely used for core-to-core communications, a topology among cores has a major impact on network latency. Therefore, in this research, to reduce end-to-end communication latency, we propose a method to build network topologies by adding multiple links between a single core and randomly selected multiple routers on a regular topology of routers. Results obtained with flit-level discrete event simulation show that our random-core-link topologies achieved the average latency up to 27% lower than that of baseline topologies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network-on-Chip(NoC) / topology / interconnection networks |
| Paper # | CPSY2013-9,DC2013-9 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/4/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A low latency topology for NoC using multiple host links |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip(NoC) |
| Keyword(2) | topology |
| Keyword(3) | interconnection networks |
| 1st Author's Name | Ryuta KAWANO |
| 1st Author's Affiliation | Graduate School of Science and Technology, Keio University() |
| 2nd Author's Name | Ikki FUJIWARA |
| 2nd Author's Affiliation | National Institute of Informatics |
| 3rd Author's Name | Hiroki MATSUTANI |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Keio University |
| 4th Author's Name | Hideharu AMANO |
| 4th Author's Affiliation | Graduate School of Science and Technology, Keio University |
| 5th Author's Name | Michihiro KOIBUCHI |
| 5th Author's Affiliation | National Institute of Informatics |
| Date | 2013-04-26 |
| Paper # | CPSY2013-9,DC2013-9 |
| Volume (vol) | vol.113 |
| Number (no) | 22 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |