Presentation | 2013-04-26 On-Chip Delay Measurement Using Adjacent Test Architecture Kentaroh KATOH, |
---|---|
PDF Download Page | ![]() |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes an on-chip delay measurement using adjacent test architecture. The adjacent Test architecture can sensitize arbitrary single sentizable path. Therefore the proposed method can sensitize more hazard free paths than conventional approach. Hence it can measure more paths with high accuracy. In addition because the proposed method sensitizes paths with subsequent single bit transition, it sensitizes more paths per a scan operation. Hence the required number of seed vector is smaller than the conventional approach. The evaluation shows that the number of vectors is 56.2% of that of enhanced scan. The number of sensitizable paths is 7.1 and 3.5 times of those of LOS and LOC measurement, respectively. The area overhead is 49.3%. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | small delay defect / delay measurement / adjacent testable flip flop / flip flop with delay fault testability |
Paper # | CPSY2013-8,DC2013-8 |
Date of Issue |
Conference Information | |
Committee | DC |
---|---|
Conference Date | 2013/4/19(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Dependable Computing (DC) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | On-Chip Delay Measurement Using Adjacent Test Architecture |
Sub Title (in English) | |
Keyword(1) | small delay defect |
Keyword(2) | delay measurement |
Keyword(3) | adjacent testable flip flop |
Keyword(4) | flip flop with delay fault testability |
1st Author's Name | Kentaroh KATOH |
1st Author's Affiliation | Department of Electrical Eng. of Tsuruoka National College of Technology Japan() |
Date | 2013-04-26 |
Paper # | CPSY2013-8,DC2013-8 |
Volume (vol) | vol.113 |
Number (no) | 22 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |