| Presentation | 2013-02-13 A Method of Acceptable Fault Identification Necessary Assignment in Logic Simplification for Error Tolerant Application Shingo MATSUKI, Junpei KAMEI, Tsuyoshi IWAGAKI, Hldeyuki ICHIHARA, Tomoo INOUE, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In error tolerant applications, some specific errors, which are of certain types or have severities within certain limits, of LSIs for such applications are tolerable In this paper, we focus on logic optimization of circuits for error tolerant apphcations[10-12] In the previous method[12], to identify removable portions of a logic circuit, the acceptability of stuck-at faults in the circuit is checked by utilizing a threshold test generation algorithm, even though this acceptability identification is time-consuming To accelerate this acceptability identification, we propose an acceptability identification procedure based on necessary assignments requires for detecting unacceptable faults Discussing the relationship between multiple acceptable faults and necessary assignments, we present an algorithm, which is faster than the test-generation-based previous algorithm, to check the acceptability of faults with an implication procedure Experimental results show that the proposed algorithm can reduce the computation effort to identify acceptable faults. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Acceptable faults / logic optimization / error significance / acceptability identification / error tolerance / necessary assignment |
| Paper # | DC2012-88 |
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| Committee | DC |
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| Conference Date | 2013/2/6(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of Acceptable Fault Identification Necessary Assignment in Logic Simplification for Error Tolerant Application |
| Sub Title (in English) | |
| Keyword(1) | Acceptable faults |
| Keyword(2) | logic optimization |
| Keyword(3) | error significance |
| Keyword(4) | acceptability identification |
| Keyword(5) | error tolerance |
| Keyword(6) | necessary assignment |
| 1st Author's Name | Shingo MATSUKI |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Junpei KAMEI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Tsuyoshi IWAGAKI |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Hldeyuki ICHIHARA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 5th Author's Name | Tomoo INOUE |
| 5th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2013-02-13 |
| Paper # | DC2012-88 |
| Volume (vol) | vol.112 |
| Number (no) | 429 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |