| Presentation | 2013-02-13 An evaluation of Trojan Circuits on AES Encryption Circuits Amy OGITA, Toshinon HOSOKAWA, Masayoshi YOSHIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Companies which specialize in LSI designs and the marketing of products without man-ufacturing LSIs are called to "fabless" The business model that fabless companies design LSIs and foundry companies manufacture LSIs recently mcreases Especially, the number of cases that LSI manufacturmg is outsourced to foreign foundry companies increases The outsourcing of LSI manufacturrig to foreign foundry companies facilitates inserting Hardware Trojan circuits into LSIs Hardware Trojan circuits are additional ones inserted into LSIs by attackers The behavior of Hardware Trojan circuits expose products to the threat such as leakages of secret information, information falsification, and circuit destruction In this paper, such a situation is assumed that LSI design partners insert Hardware Trojan circuits into design descriptions LSI design partners are defined as other companies where fabless companies outsource parts of LSI designs AES en-cryption circuits are targeted as the insertion of Hardware Trojan circuits In this paper, we pro-pose Hardware Trojan designs to leak a data relevant to an encryption key from AES encryption circuits and evaluate additional area overhead and toggle coverage compared with origmal cir-cuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | AES encryption circuits / hardware Trojan / security / design for testability |
| Paper # | DC2012-86 |
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| Committee | DC |
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| Conference Date | 2013/2/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An evaluation of Trojan Circuits on AES Encryption Circuits |
| Sub Title (in English) | |
| Keyword(1) | AES encryption circuits |
| Keyword(2) | hardware Trojan |
| Keyword(3) | security |
| Keyword(4) | design for testability |
| 1st Author's Name | Amy OGITA |
| 1st Author's Affiliation | Graduate School of lndustraal Technology, Nihon University() |
| 2nd Author's Name | Toshinon HOSOKAWA |
| 2nd Author's Affiliation | College of lndustraial Technology, Nihon Unaversaty |
| 3rd Author's Name | Masayoshi YOSHIMURA |
| 3rd Author's Affiliation | Graduate School of lnformation Science and Electrical Engineering, Kyushu Unaversity |
| Date | 2013-02-13 |
| Paper # | DC2012-86 |
| Volume (vol) | vol.112 |
| Number (no) | 429 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |