| Presentation | 2013-02-13 Accelerating techniques for SAT-based test pattern generation Yusuke MATSUNAGA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A naive way to solve ATPG problem using SAT solver is to formulate a test generation problem for a fault at a time This paper presents acceleration techniques to represent more than two test generation problems as one CNF with introducing control variables The experimental results show that the proposed techniques accelarate processing time by factor of 2-10. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test pattern generation / SAT |
| Paper # | DC2012-81 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/2/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accelerating techniques for SAT-based test pattern generation |
| Sub Title (in English) | |
| Keyword(1) | test pattern generation |
| Keyword(2) | SAT |
| 1st Author's Name | Yusuke MATSUNAGA |
| 1st Author's Affiliation | Faculty of Information Science and Electoncal Engineenng, Kyushu University() |
| Date | 2013-02-13 |
| Paper # | DC2012-81 |
| Volume (vol) | vol.112 |
| Number (no) | 429 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |