| Presentation | 2013-01-17 Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster Yoshiaki KONO, Hayato SUZUKI, Ryotaro CHIBA, Kentaro SANO, Satoru YAMAMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper reports prototype implementation and performance evaluation of a custom computing machine for the Lattice Boltzmann method (LBM) to be implemented on our tightly-coupled FPGA cluster. In general, strong scaling prevents performance from scaling with the number of computing nodes because it gets difficult to hide communication time with computing time. In our research, to solve this problem, we have proposed and developed the tightl-coupled FPGA cluster with an accelerator-domain network (ADN) to provide low-latency and high-bandwidth direct connection for FPGAs In this paper, we describe the architecute and stream computation of the LBM custom computing machine. We evaluate its performance based on prototype implementation with a single FPGA of the FPGA cluster. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-performance computation / lattice boltzmann method / accelerator-domain network / tightly-coupled FPGA cluster / FPGA |
| Paper # | VLD2012-135,CPSY2012-84,RECONF2012-89 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2013/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster |
| Sub Title (in English) | |
| Keyword(1) | high-performance computation |
| Keyword(2) | lattice boltzmann method |
| Keyword(3) | accelerator-domain network |
| Keyword(4) | tightly-coupled FPGA cluster |
| Keyword(5) | FPGA |
| 1st Author's Name | Yoshiaki KONO |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Hayato SUZUKI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Ryotaro CHIBA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Kentaro SANO |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 5th Author's Name | Satoru YAMAMOTO |
| 5th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2013-01-17 |
| Paper # | VLD2012-135,CPSY2012-84,RECONF2012-89 |
| Volume (vol) | vol.112 |
| Number (no) | 376 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |