| Presentation | 2013-01-17 Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool Yoshihiro NAKAMURA, Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we implemented a stencil computation kernel on an FPGA accelerator using MaxCompiler and MaxGenFD tools, which are a high-level synthesis compiler and its upper-layer framework. The performance evaluation results showed that an optimized system with one FPGA chip calculated 1.5e+09 grids per second, which is 21.29 and 5.08 times faster than baseline implementation and optimized CPU implementation, respectively. We also proposed and evaluated a performance estimation method for FPGA-based stencil computation. The difference between the estimated and measured performance was increased when the pipeline frequency of stencil computation was high, suggesting the pipeline stalls occurred due to the lack of data transfer throughput. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / acceleration / high-level synthesis / stencil computation |
| Paper # | VLD2012-133,CPSY2012-82,RECONF2012-87 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2013/1/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | acceleration |
| Keyword(3) | high-level synthesis |
| Keyword(4) | stencil computation |
| 1st Author's Name | Yoshihiro NAKAMURA |
| 1st Author's Affiliation | Graduate School of Engineering, Nagasaki University() |
| 2nd Author's Name | Keisuke DOHI |
| 2nd Author's Affiliation | Graduate School of Engineering, Nagasaki University |
| 3rd Author's Name | Yuichiro SHIBATA |
| 3rd Author's Affiliation | School of Engineering, Nagasaki University |
| 4th Author's Name | Kiyoshi OGURI |
| 4th Author's Affiliation | School of Engineering, Nagasaki University |
| Date | 2013-01-17 |
| Paper # | VLD2012-133,CPSY2012-82,RECONF2012-87 |
| Volume (vol) | vol.112 |
| Number (no) | 376 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |