| Presentation | 2013-01-24 Simulation and Expenmental Demonstration of Logic Circuits Using an Ultra-low-power Adiabatic Quantum-Flux-Parametron Kenta INOUE, Naoki TAKEUCHI, Kohei EHARA, Yuki YAMANASHI, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically In the present study, we designed basic AQFP gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments The AQFP 1-bit full adder is composed of 46 Josephson Junctions, which is approximately one-quarter the number of a full adder using conventional rapid single-flux-quantum logic The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8% |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | QFP / adiabatic circuits / superconducting devices / low power / energy efficiency / primitive gate / full adder |
| Paper # | SCE2012-31 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2013/1/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Simulation and Expenmental Demonstration of Logic Circuits Using an Ultra-low-power Adiabatic Quantum-Flux-Parametron |
| Sub Title (in English) | |
| Keyword(1) | QFP |
| Keyword(2) | adiabatic circuits |
| Keyword(3) | superconducting devices |
| Keyword(4) | low power |
| Keyword(5) | energy efficiency |
| Keyword(6) | primitive gate |
| Keyword(7) | full adder |
| 1st Author's Name | Kenta INOUE |
| 1st Author's Affiliation | Department of Electrical and Computer Eng , Yokohama National University() |
| 2nd Author's Name | Naoki TAKEUCHI |
| 2nd Author's Affiliation | Department of Electrical and Computer Eng , Yokohama National University |
| 3rd Author's Name | Kohei EHARA |
| 3rd Author's Affiliation | Department of Electrical and Computer Eng , Yokohama National University |
| 4th Author's Name | Yuki YAMANASHI |
| 4th Author's Affiliation | Department of Electrical and Computer Eng , Yokohama National University |
| 5th Author's Name | Nobuyuki Yoshikawa |
| 5th Author's Affiliation | Department of Electrical and Computer Eng , Yokohama National University |
| Date | 2013-01-24 |
| Paper # | SCE2012-31 |
| Volume (vol) | vol.112 |
| Number (no) | 408 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |